新工作机会分享! 急招：Senior IC Layout Engineer 

Location：Silicon Valley Santa Clara 

Duration: 3 Months contract role / with possible extension 

Experience in layout of high-speed RF / analog / mixed signal / digital block 

Knowledge of nm CMOS/ BiCMOS layout and tape-out process. 

Expert on one or more of the following: Cadence, nmDRC, Calibre, PVS, PEX, ERC, ANT, Linux layout and verification environment.  

感兴趣联系微信：yaolutingjoy, send resume to email：joy@internationalrecruit.net